Integrated circuits (ICs) can operate at two power supply voltages to minimize power consumption while improving performance. The integrated circuits used in dual voltage supply applications are typically designed to have internal or core logic which operates at one voltage level, and input/output (I/O) circuits which operate at another voltage level. The power supply voltage level used by the core logic is usually selected to be within voltage limits dictated by IC process design rules which maximize logic density. The higher power supply voltages used by the I/O circuits maximize IC drive capability or switching speed.
ICs which use dual power supplies often times require that a certain sequence be followed during activation of the supplies. This is because random application of the supply voltages to the I/O circuits and the core logic can result in unintended logic states being passed between the core logic and the I/O circuits. Even worse, catastrophic failures of the ICs can result if latch-up is triggered by the random application of the supply voltages.
One problem that can occur from unintended logic states is bus contention. Bus contention occurs at a system level when the core logic is powered-up after the I/O circuits are powered-up, and the bi-directional I/O pins driven by the I/O circuits are unintentionally configured as outputs. Typically, the control logic which selects the configuration of the I/O circuits as either inputs or outputs is located in the core logic. When the I/O circuitry is powered-up before the core logic, the input or output configuration of the I/O circuit is unknown, and bus contention can result. When the I/O pins of the IC attempt to drive other I/O pins of other external devices which are also configured as outputs, a high current condition can occur which results in physical damage of the IC.
Another problem that can occur from random application of the supply voltages to the I/O circuits and the core logic is the corruption of data stored within the IC. This occurs when stored logic states within the core logic are unintentionally changed.
Random application of the supply voltages can result in reduced performance levels if the power supplies provide supply voltages at different points in time. This is because ICs which operate at two supply voltages are usually not operated until the possibility of unintended logic states occurring is minimized, which is after both of the supply voltages are valid.
In view of the above, there is a need for a sequencing system which improves performance and reduces the possibility of data loss or damage to the IC resulting from random application of the supply voltages to the IC.